LONGEST SIGNAL PATH FOUR BIT OR PORTABLE

Another approach to improve read stability is the use of a separate path for reading operation. Some techniques reported for improving write noise margin are – WL boosting ], power cut-OFF ], raising the cell Vss ], and negative bit-line (NBL). Many SRAM cell designs have been proposed in the literature, solving one or multiple challenges mentioned above - ]. So it is challenging to maintain the cell stability and therefore, read and write failure probabilities are considerably increased in the conventional 6T SRAM under lower supply voltages ]. Static noise margin degrades linearly as the supply voltage is scaled down because it has an exponential relationship with threshold voltage ]. As technology entered into the sub-100 nm regime, threshold voltage, leakage current and process, voltage and temperature (PVT) variations are of serious concern. Furthermore, the scaling of supply voltage degrades the performance ]. However, MOSFETs undergo short channel problems in scaled technologies, especially in the sub-threshold region, which also leads to increased sensitivity to process variation in these devices ]. Many researchers have designed logic circuits in the sub-threshold region to gain the benefits of the supply voltage scaling scheme. The scaling of supply voltage reduces both leakage and dynamic powers. Supply voltage scaling is one of the popular techniques to reduce power consumption ]. Low power static random access memory (SRAM) is particularly important because of a major portion of the system on chip is occupied by them ].

LONGEST SIGNAL PATH FOUR BIT OR PORTABLE

The demand for portable applications such as mobile phones, laptops, and medical devices like pacemaker, defibrillator, and pedometer require ultra-low power in integrated circuits. The cell provides write delay improvement from 29.77 to 49.40% and read delay improvement from 7 to 12% compared to 9T, 10T, and PG9T, respectively. The proposed cell exhibits higher write and reads static noise margins with an improvement of 13.54 and 63.28%, respectively, compared to conventional 6T SRAM cell.

In standby mode, from 6.71 to 7.37% leakage power reduction is observed for this cell at an operating voltage of 1.2 V and 29.21 to 58.68% & 32.74 to 71.11% improvement for write & read power over other cells. To show the effectiveness of the cell, its design metrics are compared with other published SRAM cells, namely, conventional 6T, 10T, 9T, and power-gated 9T (PG9T). The cell also achieves low power due to the stack effect.

Furthermore, it solves the row half select disturbance and utilises a row-based virtual ground signal to eliminate unnecessary bit-line discharge in the un-selected row, thus decreasing energy consumption. The proposed cell has a separate read and write path which successfully improves read and write abilities. This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation.

IET Generation, Transmission & Distribution.

IET Electrical Systems in Transportation.

IET Cyber-Physical Systems: Theory & Applications.

IET Collaborative Intelligent Manufacturing.

CAAI Transactions on Intelligence Technology.

Longest signal path four bit or